1. Field of the Invention
The present invention relates to an error correcting method and an apparatus therefor, and in particular to a method and an apparatus for performing an error correction of a transmission signal with a Hamming code.
In a long distance transmission line of an optical transmission equipment by way of example, a loss caused by an optical fiber is compensated by the cascade connection of optical amplifiers, while a noise generated at each of the optical amplifiers deteriorates network quality parameters, e.g. a BER (Bit Error Rate).
As an efficient method to solve this problem, an error correcting method and an apparatus therefor are required by a transmitter making a message an error correcting code to be transmitted and a receiver detecting an error bit included in a received message to correct the bit.
2. Description of the Related Art
(1) It is known as a prior art error correcting method that for example, in xe2x80x9cDesign and Characterization of an Error-Correction Code for the SONET STS-1 Tributaryxe2x80x9d published in the IEEE TRANSACTIONS ON COMMUNICATION. VOL.38. NO.4 APRIL 1990, a Forward Error Correction (hereinafter occasionally abbreviated as FEC) is performed with a TOH portion (an SOH portion, an LOH portion) and a payload portion except the LOH portion within a single frame being allotted for an operation area by using a shortened Hamming code, and with Z3 and Z4 byte portions in a POH portion being allotted for check bits.
(2) Additionally, in xe2x80x9cA forward error correcting scheme for SONET 10 Gb/s Optical Transmission systemxe2x80x9d published in the T1X1.5/94-148 July 12th 1994 (ALCATEL NETWORK SYSTEM), the FEC is performed with the LOJ portion except the SOH portion and the payload portion within a single frame being allotted for the operation area by using the shortened Hamming code, with a single frame being divided into three, i.e. 9th, 1st, 2nd rows, 3rd-5th rows, and 6th-8th rows, with the check bits of the 9th, 1st and 2nd rows being allotted for a D3 byte portion of the SOH portion, with the check bits of the 3rd-5th rows being allotted for a D6 byte portion of the LOU portion, and with the check bits of the 6th-8th rows being allotted for an E2 byte portion of the LOH portion.
(3) Moreover, in xe2x80x9cFORWARD ERROR CORRECTION FOR SUBMARINE SYSTEMSxe2x80x9d published in the ITU-T (TELECOMMUNICATION STANDARDIZATION SECTION OF ITU) Recommendation G.975 (11/96), the FEC is performed with the whole of a single frame being allotted for the operation area by using an RS (Reed-Solomon) code, and with an increased part of a transmission speed being allotted for the check bits.
(4) Furthermore, in an error correcting/encoding method and a transmitter/receiver apparatus published in the Japanese Patent Publication Laid-open No.9-130355, the FEC is performed with the payload portion except the TOH portion within a single frame being allotted for the operation area by using the RS code, with a single frame being divided into two, and with non-defined byte portions in the LOH portion being allotted for the check bits.
By the error correcting method (1), since at least a single frame has to be held in a memory once, a transfer delay becomes 139 xcexcseconds (=125 xcexcsecondsxc3x97900 bytes/810 bytes). This value does not satisfy the standard of transfer delay, i.e. equal to or less than 100 xcexcseconds prescribed by ANSI T1.506A-1992, Telecommunication Performance-Specifications for Switched Exchange Network (Absolute, Round-trip Delay), ANSI T1.508-1992.
Also, by the error correcting method (2), since the SOH is used for the check bits and the SOH is terminated in case that a regenerator or relaying equipment is positioned on a transmission line, the FEC can not be performed.
Moreover, by the method (3), since the transmission speed is increased for the addition of the check bits, the apparatus executing this method is not based on the SONET and therefore an SDH is only used in an isolated state from the world standard.
Generally, what kind of error correcting codes can efficiently perform the error correction depends on an error occurrence pattern on a transmission equipment, a system, and a transmission line.
The error correcting methods (3) and (4) use the RS code. The RS code is suitable for the system where a burst error is generated. When the RS code is adopted for such a system, the BER is highly improved as compared with the case of the Hamming code.
However, the RS code requires a memory on the transmitter side and enlarges a circuit scale. Furthermore, assuming that the number of bits in one character is xe2x80x9cnxe2x80x9d, the RS code notifies that the number of errors is xe2x80x9c1xe2x80x9d in case the number of error bits is any one of 1 to n. Accordingly, the RS code can not accurately count the number of error bits.
Moreover, by the method (4), the transmission speed is an integer times of 622.08 Mb/s. In this case, compared with the case using the Hamming code, the higher the transmission speed, the larger the difference of both circuit scales.
In an optical transmission equipment or the like, it is required that the deterioration of BER by an optical amplifier is prevented and the frequency of switchover by an SD (Signal Degrade: a random error of 1xc3x9710xe2x88x922xe2x88x9210xe2x88x929 rate) is decreased.
Generally, the Hamming code is suitable for a random error correction, and can accurately notify the number of corrected bits. The circuit scale for the Hamming code is smaller compared with that for the RS code since on the transmitter side of the CRC operation of information bits is performed and the result only has to be inserted into the check bits, eliminating any need of memory.
It is accordingly an object of the present invention to provide an error correcting method and an apparatus therefor using a Hamming code wherein the transfer delay is reduced, the BER is improved, and the circuit is small-scaled.
In order to achieve the above-mentioned object, an error correcting method according to the claim 1 divides a frame prescribed for a synchronous network into L Hamming code blocks, where L is a natural numberxe2x89xa69, in a direction of row and allots information bits and check bits to each of the blocks.
Namely, the Hamming code is required to temporarily hold all of the information on a receiver side when an error correction is performed. The transfer delay is caused for the holding time. By dividing a single frame into L Hamming code blocks and making the size of a single Hamming code block 1/L of a single frame, the transfer delay is reduced.
In the present invention according to the claim 2, the synchronous network may comprise SONET or SDH, and the frame may comprise an STS-N frame, an OC-N frame, or an STM-N frame.
Namely, the synchronous network may be either the SONET or the SDH, and the frame may adopt either the STS-N frame or the OC-N frame prescribed by the SONET, or may adopt the STM-N frame prescribed by the SDH.
In the present invention according to the claim 3, the information bits and the check bits may be allotted to a payload portion of the frame and non-defined bits of an LOH portion, respectively.
Namely, the information bits are allotted to the payload portion, while they are not allotted to the SOH portion and the LOH portion including B1 and B2 byte portions which have a possibility of being rewritten during transmission. The check bits are allotted to the non-defined bits of the LOH portion, while they are not allotted to the SOH portion terminated in a relaying equipment. Accordingly, an FEC can be performed without the Hamming code blocks being rewritten during transmission and being terminated at the relaying equipment.
In the present invention according to the claim 4, the information bits and the check bits may be further divided into M subblocks, where M is a natural numberxe2x89xa72, to compose the Hamming code block having a single subblock of the information bits and the check bits.
Namely, the Hamming code blocks composed of the information bits and the check bits are divided into M subblocks. Lxc3x97M subblocks are made to the Hamming code blocks, and a code length, i.e. information bit number can be shortened.
As a result, it becomes possible to make simple the composition of a primitive polynomial for selecting a generation polynomial required on transmitter/receiver sides with fewer degrees, for e.g. an easy simulation.
In the present invention according to the claim 5, the information bits and the check bits may be rearranged per bit over each of the Hamming code blocks in order that an error correction of sequential M bits is made.
Namely, the Hamming code is suitable for a random error correction, so that only a single bit error within a single Hamming code block can be corrected. Accordingly, a burst or sequential bit error can not be corrected.
For this reason, burst error bits generated in a single Hamming code block are to be scattered into M Hamming code blocks. Namely, the information bits and the check bits are respectively rearranged in order that only a single or null error bit may exist in each of the Hamming code blocks.
As a result, it becomes possible to correct the burst error bits of sequential M bits, further improving the BER.
Moreover, in order to achieve the above-mentioned object, an error correcting apparatus according to the claim 6 may comprise a code error correcting means for dividing a frame prescribed for a synchronous network into L Hamming code blocks, where L is a natural numberxe2x89xa69, in a direction of row and for allotting information bits and check bits to each of the blocks.
Namely, when the error is corrected on the receiver side, the Hamming code requires a shift register which temporarily holds block information of a single Hamming code. The transfer delay is caused for the holding time.
Therefore, by dividing a single frame into L Hamming code blocks and making the size of a single Hamming code block 1/L of a single frame, it becomes possible to small-scale the circuit and to reduce the transfer delay.
In the present invention according to the claim 7, the synchronous network may comprise SONET or SDH, and the frame may comprise an STS-N frame, an OC-N frame, or an STM-N frame.
In the present invention according to the claim 8, the code error correcting means may allot the information bits and the check bits to a payload portion of the frame and non-defined bits of an LOH portion, respectively.
Namely, small-scale and identical circuits for the Hamming code only have to be required for allotting the information bits to the payload portion divided into L, and even when there is the relaying equipment on a transmission line, the FEC can be performed by allotting the check bits to the non-defined bits not of the SOH portion which is terminated in the relaying equipment but of the LOH portion.
Namely, the information bits are allotted to the payload portion but neither to the SOH portion nor LOH portion including the B1 and B2 byte portions which have a possibility of being rewritten during the transmission. The check bits are allotted to the non-defined bits of the LOH portion, but not to the SOH portion terminated in the relaying equipment. Accordingly, the FEC can be performed without the Hamming code blocks being rewritten during the transmission and being terminated at the relaying equipment.
In addition, since the information bits are divided into L and are allotted to the payload portion, the circuits which process the payload portion can be used as L equivalent processing circuits.
In the present invention according to the claim 9, L may be equal to 3, and the code error correcting means may allot three blocks of 9th, 1st, 2nd rows, 3rd-5th rows, and 6th-8th rows in the payload portion to the Hamming code blocks and may allot the check bits of each Hamming code block to K1, D5 and Z2 byte portions which are the non-defined bits in the LOH portion.
Namely, the payload portion is divided into three blocks, i.e. 9th, 1st, 2nd rows, 3rd-5th rows, and 6th-8th rows. These three Hamming code blocks are composed of the information bits allotted to each of the blocks and the check bits allotted to the K1 byte portion of the 5th row, the D5 byte portion of the 6th row, and the Z2 byte portion of the 9th row in the LOH portion.
By allotting the Hamming code blocks in this way, the receiver side can perform a code error correction only with a memory for five rows at the maximum. The transfer delay is 69.4 xcexcseconds (=125 xcexcsecondsxc3x975 rows/9 rows), which satisfies the above-mentioned standard, i.e. equal to or less than 100 xcexcseconds.
In the present invention according to the claim 10, the code error correcting means may divide the information bits and the check bits into M subblocks, where M is a natural numberxe2x89xa72, to generate the Hamming code blocks having the Hamming code to compose a single subblock of the information bits and the check bits.
Namely, the Hamming code blocks are remade by dividing the Hamming code blocks composed of the information bits and the check bits into M subblocks, thereby shortening the code length of a single Hamming code block.
As a result, it becomes possible to make simple the composition of a primitive polynomial for selecting a generated polynomial required on the transmitter/receiver sides with fewer degrees and to small-scale the circuit for an easy simulation.
In the present invention according to the claim 11, the code error correcting means may include data exchanging means for rearranging the information bits and the check bits per bit over each of the Hamming code blocks in order that an error correction of sequential M bits is made.
Namely, the data exchange means rearrange sequential M burst error bits generated in a sequential single Hamming code block in order that each of M Hamming code blocks may have a single bit of the error bits. Accordingly, the error bit of each Hamming code block is a single bit at most so that the error correction is made possible.
As a result, the burst error bits correction of sequential M bits can be performed and the BER can be improved.
In the present invention according to the claim 12, the code error correcting means may include syndrome registers, composed of a plurality of banks, which divide a received Hamming code message per the Hamming code block, operate a syndrome of each Hamming code block, and make a code error correction of each Hamming code block based on the operation result by changing the banks.
Namely, the syndrome registers read the information bits and the check bits of the received Hamming code block to operate the syndrome. Based on the operation result, the error bits included in the Hamming code blocks are corrected.
Accordingly, a start time for processing the next Hamming code block is delayed with single syndrome registers, which makes it difficult to follow the transmission speed of frame.
For this reason, the syndrome registers composed of a plurality of banks is prepared. The received Hamming code message is divided per a Hamming code block, and the syndrome registers sequentially operate the syndrome of each Hamming code block in parallel to hold the result.
Based on the operation result, the code error correction of each Hamming code block can be performed. The syndrome registers having completed a series of these operations successively shift to the processing of the next Hamming code block.
As a result, the transfer delay of the frame can be reduced.
In the present invention according to the claim 13, the code error correcting means may include syndrome registers which operate the check bits by sequentially repeating searches for output states in parallel at a time t+x from an information vector and the output state at a time t, with the information vector at each time being formed of sequential x transmitting information bits of a transmitting message.
In the present invention according to the claim 14, the code error correcting means may include syndrome registers which operate a syndrome by sequentially repeating searches for output states in parallel at a time t+x from an information vector and the output state at a time t, with the information vector at each time being formed, every x bits, of a received Hamming code message.
Namely, on both of the receiver and transmitter sides, the syndrome registers are assumed to have a parallel input and a parallel output. Sequential x bits of the transmission message are converted into parallel data per time interval x as an information vector of the time t.
From this information vector and the output states of the syndrome registers at the time t, the output states of the syndrome registers at the time t+x are operated to latch the result of the operation in the syndrome registers with the timing of t+x. By repeating these operations, the check bits or the syndrome is outputted in parallel to the output terminals of the syndrome registers.
Namely, the processing of converting the transmission message into the error correcting code or of performing the error correction of the received message can be performed for x bits in parallel.
As a result, by delaying the processing speed of the frame with a high transmission speed up to the speed applied to an LSI used for the error correcting code, an operation margin of the LSI can be secured.
In the present invention according to the claim 15, the code error correcting means may include syndrome registers which can correct a single bit error of the received Hamming code message and detect an even bit error, and detecting means for outputting a single bit error correcting signal and an even bit error detecting signal.
Namely, the syndrome registers are composed in order that a single bit error correction and an even bit error detection for the received Hamming code message may be performed. The detecting means output a signal indicating that a single bit error correction has been performed and even bit errors have been detected based on the output signals of the syndrome registers.
As a result, the error bit number occurred in the Hamming code can be counted, enabling to recognize how the BER is improved.
In the present invention according to the claim 16, the code error correcting means may further include encoding setting means which designate a start and a finish of a Hamming-encoding on the transmitter side.
Basically, the FEC functions on the transmitter/receiver sides are required to operate in cooperation with each other.
In addition, when the receiver side has no FEC function, the FEC function on the transmitter side is required to be set as xe2x80x9cfinishxe2x80x9d. When the encoding setting means designate the xe2x80x9cfinishxe2x80x9d for Hamming-encoding, the code error correcting means do not perform the FEC operation to fulfill the requirements.
In the present invention according to the claim 17, the encoding setting means set predetermined non-defined byte portion of an LOH portion to an eigen value when the start of the Hamming-encoding is designated, and sets the check bits to all xe2x80x9c0xe2x80x9d or all xe2x80x9c1xe2x80x9d when the finish thereof is designated.
Namely, it is required on the transmitter side to notify the receiver side whether or not the transmitted message is Hamming-encoded. If it is the case, the transmitter side notifies the receiver side of the Hamming-encoding by transmitting the fixed non-defined byte portion in the form of the eigen value.
In addition, there is a fixed standard in which non-used byte portion have to be set to either all xe2x80x9c0xe2x80x9d or all xe2x80x9c1xe2x80x9d. In accordance with this fixed standard, for the case of the xe2x80x9cfinishxe2x80x9d designating that the Hamming-encoding is not performed, the check bits can be set to either all xe2x80x9c0xe2x80x9d or all xe2x80x9c1xe2x80x9d designated by the standard.
In the present invention according to the claim 18, the code error correcting means may include decoding setting means which designate a start or a finish of decoding the Hamming code on the receiver side.
Namely, when the transmitter side has no FEC function or when the message is transmitted without Hamming-encoding, it is required that the FEC function is not performed on the receiver side. Therefore, the decoding setting means designate the finish of decoding to fulfill the requirement.
In the present invention according to the claim 19, the decoding setting means may include means for designating a start and a finish of decoding action with either a compulsory start or a compulsory finish, and starts a decoding action only when the designation is the compulsory start or the compulsory finish, the value of the check bits is neither all xe2x80x9c1xe2x80x9d nor all xe2x80x9c0xe2x80x9d, and the predetermined non-defined byte portion of the LOH portion have an eigen value.
Namely, when examining the apparatus, a forced setting of the start of the FEC function is required.
For this requirement, when the decoding setting means designate the forced start, the FEC function is performed to enable the examination.
In addition, when the forced finish is designated on the contrary, the decoding is performed only when the check bits are neither all xe2x80x9c0xe2x80x9d nor all xe2x80x9c1xe2x80x9d indicating that the check bits are not used, that is indicating that the Hamming-encoding is not performed to the message, and predetermined non-defined bits of the LOH portion has an eigen value indicating that the Hamming-encoding is performed.
In the present invention according to the claim 11, the code error correcting means may include means for a BIP-Nx24 operation by B2 byte information of an LOH portion after Hamming-encoding a transmitting message.
When the transmitter side has the FEC function and the receiver side has no FEC function and the FEC function on the transmitter side is mistakenly performed, an error occurs on the receiver side in order of the FEC function and the B2 byte function on the transmitter side.
For example, when the FEC function is performed after the B2 byte operation, a B2 byte error occurs when the B2 byte operation is performed without performing the FEC function on the receiver side because FEC error correcting bytes are included in the operation range of the B2 byte portion.
For this reason, the transmitter/receiver sides solve this problem by performing the B2 operation after the FEC function.
In the present invention according to the claim 12, the code error correcting means may include means for a BIP-Nx24 operation by B2 byte information of an LOH portion after correcting the Hamming code error of a received message.
Namely, after the error correction of the Hamming code of the received message is firstly corrected, the B2 operation of the received message with the error corrected is performed.
As a result, the BER is improved in the B2 operation, so that the number of a line switchover frequency by the SD alarm can be reduced.